1. Field of the Invention
The present invention relates to integrated circuit memory systems, and more particularly to cache memory systems.
2. Description of the Related Art
In typical hierarchical memory systems, cache memories are small, fast memory circuits that store most-recently accessed code or data to reduce the latency (i.e., the total time between the start and completion) of references to memory. As integrated circuit die sizes increase and integrated circuit manufacturing process geometries decrease, the size of a cache memory that may be implemented on an integrated circuit die increases, e.g., 100 megabytes (MB) or greater. In an exemplary processor architecture, a cache memory occupies a substantial portion of the processor area and the ratio of cache memory area to core logic area may increase in the future.
In general, as cache memory size increases, the total power dissipation (i.e., static power dissipation, e.g., power dissipation due to leakage current or other current drawn continuously from the power supply, and dynamic power dissipation, e.g., power dissipation due to switching transient currents and/or charging and discharging of load capacitances) of the cache memory increases, which typically reduces battery life in portable applications. As cache memory sizes increase and gate sizes decrease, static power dissipation increases and may become a larger portion of total power dissipation.